Modern electronic equipment of all types, especially computing and communication equipment, depends more and more on microprocessors and digital logic circuitry to attain performance levels desired by consumers. Microprocessors and logic circuits generally require clock signals or timing signals for proper operation.
In order to provide the necessary timing and control information to a microprocessor or logic circuit, a clock signal must generally be a square wave signal with amplitude excursions that come as close as possible to the supply voltage at the point of maximum excursion, and ground potential at the point of minimum excursion. Of course, high amplitude square wave signals are difficult to distribute within communication equipment in particular, because square waves have a high harmonic content that can cause interference with adjacent circuitry.
In practice, it is common to distribute low amplitude sinusoidal a.c. (alternating current) clock signals to circuitry that may be sensitive to interference from square wave harmonics. Sensitive circuits of this type include frequency synthesizers used in communication equipment. One solution to this problem is to provide separate distribution systems for system timing signals.
This dual distribution concept gives rise to several potential problem areas. First, a method must be found for deriving high amplitude square wave clock signals from low-level a.c. input signals, so that the square wave clock and the a.c. signal will be the same frequency; having the frequencies be identical is important in many applications. It is also frequently important that the duty cycle of the square wave clock and the a.c. input signal be the same. Of course, noise immunity is virtually always an important design constraint, as well.
Size and power consumption are also important design considerations in any clock signal distribution scheme. With electronic equipment becoming smaller and smaller, and battery operation becoming a more popular feature, there is often little space or power to spare.
Prior designs have attempted to solve some of the problems set forth above. FIG. 1 illustrates one example of a squaring amplifier of the prior art, as generally depicted by the numeral 100. In this circuit, an a.c. input signal (101) is a.c. coupled through a capacitor (102) to the input of an inverter. The inverter consists of two complementary FET's (field effect transistors) (103 and 104) and is powered by a d.c. (direct current) supply voltage (105). A resistor (109) connects the input of the inverter to the output of the inverter (106). This resistor provides a quiescent operating point for the two transistors (103 and 104) The post-coupled input signal then has a d.c. potential that is at the cross-over threshold of the inverter. The drain current of each FET (103 and 104) is proportional to the square of its gate-to-source voltage. However, in the way that these element are connected in FIG. 1, the output current at the junction of the two FET's (106) is a linear function of the input voltage at their gates. As the input voltage increases, the p-channel FET's (103) drain current decreases and the n-channel FET's (104) drain current increases. The difference in these drain currents is the output (106). This current discharges the input capacitance of a load inverter (107). When the voltage on the input capacitance of the load inverter (107) falls below the inverter's threshold, the inverter's output goes to its high potential. When the voltage at the input of a subsequent inverter (108) goes above the inverter's threshold, the inverter's output goes to its low potential. These first inverters (107 and 108) and any subsequent inverters provide additional gain to produce a substantially rectangular output. When the input voltage decreases, the current flow at the junction node (106) is in the opposite direction, and outputs that are the converse of those discussed above occur. As the a.c. input signal transitions through the quiescent point, transitions are produced at the output of the second inverter (108) that is a substantially rectangular waveform. It is desirable that device geometries (103 and 104) be as large as possible to minimize noise effects. However, large device geometries increase current consumption when small a.c. input signals are applied.
Another prior art squaring amplifier is shown in FIG. 2 (and generally depicted by the numeral 200). In this circuit, an a.c. input signal (201) is a.c. coupled through a capacitor (202) to the input of an inverter. The inverter consists of two complementary FET's (203 and 204) and is powered by a d.c. supply voltage (205). A current source (206) is placed in series with the inverter (203 and 204) to limit the quiescent current consumption. A resistor (207) connects the input of the inverter to the output of the inverter. This resistor provides a quiescent operating point for the two transistors (203 and 204). The post-coupled input signal then has a d.c. potential that is at the cross-over threshold of the inverter (203 and 204). The drain current of each FET (203 and 204) is proportional to the square of its gate-to-source voltage. However, in the way that these elements are connected in FIG. 2, the output current at the input to inverter 208 is a linear function of the input voltage at the gates of 203 and 204 within the a.c input voltage range. As the input voltage increases, the p-channel FET's (203) drain current decreases and the n-channel FET's (204) current increases. The difference in these drain currents is the input to the inverter (208). This current discharges the input capacitance of the load inverter (208). When the voltage on the input capacitance of the load inverter (208) falls below the inverter's threshold, the inverter's output goes to its high potential. When the input voltage decreases, the current flow charges the input capacitance of the load inverter (208). When the voltage on the input capacitance of the load inverter (208) goes above the inverter's threshold, the inverter's output goes to a low potential equal to the source voltage of FET 204 which is determined by the current source (206). As the a.c. input signal transitions through the quiescent point, transitions are produced at the output of inverter (208) that is a substantially rectangular waveform. However, the substantially rectangular waveform does not reach ground potential. Level shifter circuitry (209) accepts the outputs of the FET combination (203 and 204) and the inverter (208) and increases the output waveform's voltage range to a maximum of the d.c supply voltage (205) and a minimum value of ground potential. The output of the level shifter, a substantially rectangular waveform, is further buffered by another inverter (210) to provide faster transition times in the waveform at the output (211). It is desirable that device geometries (203 and 204) be as large as possible to minimize noise effects. The addition of the current source (206) limits the current consumption of the circuit when a small a.c. input signal is applied, but requires the addition of the level shifting circuit (209) to produce the desired substantially rectangular output waveform.
It can thus be appreciated that squaring amplifier circuits of the prior art fall short of meeting design criteria dictated by electronic equipment in which small-size, low-power circuitry is desirable. Accordingly, a need arises for a squaring amplifier circuit producing a substantially rectangular output in response to a low-level a.c input signal, while ensuring that the output frequency and duty cycle duplicate that of the input signal. In addition, the squaring amplifier should occupy minimal space and use little power.